Radio frequency laterally diffused metal oxide transistors (RF LDMOS) are widely employed in the domain of high power radio frequency transmission for base stations and radio and television transmission. They adopt power arrays and synthesis of multi chips to attain a power output of over 500 w. Hence, a major aspect for improving product properties is to increase the power density per gate width. While with a higher power density, the gate width required for a single chip (unit cell) power will be relatively low, and hence the parasitic capacitance of the overall device will be reduced, and the other radio frequency properties of the device, such as efficiency and gains, will be elevated.
FIG. 1 shows a schematic diagram of a radio frequency LDMOS device of the prior art, exemplified with an N type device, which comprises: a P type heavily doped, that is, a P+ doped silicon substrate 101, the doping concentration thereof being greater than 1 e20−3; a P type lightly doped silicon epilayer 102, the doping concentration and width thereof being dependent on the working voltage of the drain of the device, the higher the working voltage of the drain, the lower the doping concentration of the silicon epilayer 102, and the greater the width; an N type drift region, formed on the silicon epilayer 102; a P type doped body region 104; a gate media layer 107 and a polysilicon gate 108; an N type heavily doped, that is, an N+ heavily doped source region 105 and drain region 106; a P+ region 112 formed in the body region 104 and leading forth a grid electrode from the body region 104; a first shielding media layer 109a and a first Faraday shielding layer (G-shield) 110a covering on a step of a lateral surface of the drain side of the polysilicon gate 108; a second shielding media layer 109b and a second Faraday shielding layer 110b covering on a step of the first shielding media layer 109a; a deep contact hole 111, which is composed of a metal, such as tungsten, filled in a deep trench sinker passing through the source region 105, the body region 104, and the silicon epilayer 102 and entering into the silicon substrate 101, and which electrically connects the source region 105, the body region 104, the silicon epilayer 102 and the silicon substrate 101.
The device as is shown on FIG. 1 adopts a double layer Faraday ring, that is, the Faraday shielding layers 1101 and 110b, is applicable for a device with 50 v bias voltage, and requires a breakdown voltage exceeding 110 v. The Faraday shielding layer functions as a field plate, reduces the electric field intensity, and increases the breakdown voltage of the device, in addition to reducing the parasitic capacitance between the drain and the gate. As can be inferred from FIG. 1, the electric field on the bottom of the double layer Faraday shielding layer will be subdued. For an evenly doped drift region 103 of the prior art, increased impact ionization takes place in the drift region 103 approximate to the peripheral of the second Faraday shielding layer 110b, and as the electric field is unevenly distributed, the comparatively strong electric field and comparatively increased impact ionization at this location will reduce the breakdown voltage of the overall device. A breakdown voltage exceeding 110 v can only be realized in the prior art via reduction of doping concentration of the drift region 103, that is, the drift region 103 is relatively lightly doped, leading to a weaker saturation current of the device, and hence a correspond lower power density, due to a strong correlation between the power density and the saturation current.